We are seeking a highly skilled and experienced ASIC Architect to lead the miniaturization of a state-of-the-art probabilistic computing platform. This is a unique opportunity to take ownership of the ASIC architecture for a probabilistic computing processor, managing the process end-to-end—from algorithm and instruction set architecture (ISA) through partitioning, microarchitecture, and tape-out. If you are passionate about cutting-edge technology and thrive in a challenging, innovative environment, we encourage you to apply.
Responsibilities:
- Conduct requirements analysis to define system needs.
- Develop a deep understanding of system-level algorithms and engage in hardware/software co-design, including arithmetic implementation in hardware.
- Analyze programmability, fixed functions, hardware implementation, and host requirements.
- Perform functional simulation and build models to inform architectural decisions.
- Define system-level architecture and ISA, translating workloads into system architecture and dataflow models.
- Conduct trade-off analysis (timing, power, area) and own partitioning with physical design awareness.
- Develop detailed specifications for microarchitectures, including:
- Memory hierarchy
- On-chip and inter-chip connectivity
- Interfacing with the analog domain and software
- Oversee internal IP development and evaluate third-party IP.
- Lead the design process through verification, signoff, tape-out, and bring-up.
Qualifications:
- Proven architectural ownership of at least one ASIC successfully taken to tape-out, preferably in compute accelerators, inference engines, or DSPs.
- Hands-on experience in performance modeling (using Python, C++, or equivalent), trade-off analysis, and simulation that directly influenced architectural decisions.
- Proficiency with industry-standard tool flows (e.g., Synopsys, Cadence, or Siemens).
- A solid understanding of timing, power, and area trade-offs at the architectural level.
- Experience defining hardware/software interfaces and collaborating with firmware and compiler teams.
- Strong RTL design expertise and the ability to define verification strategies at the architectural level.
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